Princeton Institute for Computational Science and Engineering (PICSciE) Exploiting Parallelism For Intel Xeon Processors & Phi Coprocessors - Talk 1 - ADDED

Session 1 – Intel Compilers Optimizations & Phi Programming Models

Do you want to learn how to take advantage of highly parallel computation capabilities offered by Intel Xeon processors and Intel Xeon Phi coprocessors? Intel software development tools makes it easy to exploit parallel performance by using consistent parallel programming models and optimization techniques. Technical consulting engineers from Intel Corporation will be providing training on Intel software development tools in two session. Session 1: Rapidly growing parallelism offered by Intel multi-core processors and many-core coprocessors will be discussed, with emphasis on both thread & SIMD- level parallelization. Intel compilers’ easy to use optimization features such as vectorization, IPO, PGO, and Cilk Plus will be presented. Learn how to program Intel Xeon Phi Coprocessors, using different programming models – native, off-load, and symmetric. Both synchronous and asynchronous offload-modes will be discussed with examples.

Date & Time

January 30, 2014 | 10:30am – 1:00pm

Location

Princeton University, 346 Lewis Science Library

Speakers

JD Patel

Affiliation

Intel