TITLE & ABSTRACT ADDED - We have witnessed a rapid evolution of computing architectures due to power constrains in the last decade. Understanding how to efficiently utilize these systems in the context of demanding numerical algorithms is an urgent task for many application scientists. In this talk, we describe approaches we use to develop a highly scalable particle-in-cell (PIC) code across one of the broadest sets of computer architectures, including multicore CPU, GPU and Intel Xeon Phi. In particular, we describe our “lessons learned” and “best practices” in optimizing PIC algorithm on Knights Landing (KNL), the 2nd generation Intel Xeon Phi processor.
Princeton University Astroplasmas Seminar
Particle-In-Cell Optimization on Multi/Many-core Architectures
Princeton Institute for Computational Science & Engineering (PICSciE) and Intel Parallel Computing Center (IPCC)
Date & Time
May 19, 2017 | 12:30 – 1:30pm